The present invention relates generally to power converters. More particularly, the present invention relates to gain enhancement circuitry for LLC resonant power converters wherein a hold-up time may be increased with minimal effect on efficiency.
As market requirements for high efficiency have become more demanding, LLC resonant converters have correspondingly grown in popularity due to their high efficiency performance and their ability to achieve high power density. The 80 Plus Platinum certification standard requires greater than 94% efficiency at half load (50%) conditions. The 80 Plus Titanium standard requires 96% efficiency at half load conditions.
However, there is a trade-off between the high efficiency and long hold-up time performance in a resonant converter. Generally speaking, the hold-up time of a converter is the amount of time (typically in milliseconds) that a power converter can continue to generate output within a specified range after an input power interruption. Efficiency can be increased significantly with, for example, an increase in magnetizing inductance to reduce switching losses. However, the hold-up time will consequently decrease by a significant amount as well. And likewise, efficiency may be sacrificed for long hold-up time performance.
One solution that is known in the art for maintaining high efficiency performance while achieving long hold-up time is to increase the bulk capacitance. However, this results in problems of low power density and also higher cost.
It would therefore be desirable to provide power converters with circuitry for balancing high efficiency and long hold-up time, while addressing the power density issues which would otherwise result from solutions in power converters as are presently known to those of skill in the art.